1. Field of the Invention
This invention relates generally to toggle flip-flops and, more particularly, to an improved emitter function logic (EFL) toggle flip-flop which requires fewer components and isolation tubs, and as a result, is faster, has a high maximum frequency capability, and occupies less space.
2. Description of the Prior Art
Emitter function logic (EFL) is a relatively new family of logic circuits based on a non-inverting gate structure and designed for large scale integration. It combines the advantages of multi-emitter structures with the performance of emitter coupled logic (ECL). A detailed description of emitter function logic may be found in an article by Z. E. Skokan entitled "Emitter Function Logic--Logic Family for LSI" which appeared in the IEEE Journal of Solid State Circuits, October 1973, page 356.
A known EFL master-slave delay type flip-flop includes first and second biased transistors in both the master and slave portions. The circuit includes a D input and generates only a Q output. In order to provide a Q output the first bias transistors in both the master and slave portions, which are dual emitter devices, are split into separate devices and an additional load resistor is added. This requires an additional isolation tub.
Once the Q output is made available, the master-slave delay type flip-flop may be converted to toggle flip-flop by simply coupling the Q output into the D input. Once this is accomplished, the toggle flip-flop will act as a frequency divider and will produce a signal having a frequency which is one-half that of the applied clock signal.